1. Field of the Invention
This invention relates to an electrically rewritable and non-volatile semiconductor memory device (EEPROM) and an electric device with the same.
2. Description of Related Art
Currently known EEPROMs are mostly formed of memory cells with floating gates for storing data charge. A cell array of a NAND-type flash memory, which is known as one of such the EEPROMs, is formed of NAND cell units arranged therein, each of which has a plurality of memory cells connected in series. Source and drain diffusion layers of the memory cells in the NAND cell unit are shared with adjacent cells. To increase the capacity of the NAND-type flash memory, it is effective to increase the number of cells in the NAND cell unit, thereby increasing the capacity of a block defined as a group of a plurality of NAND cell units sharing a word line with them.
If only a small amount of data is written in a block of the NAND-type flash memory, the remaining area of the block becomes wasteful. In consideration of this point, in practice, one block is often divided into some file areas, and the data control is performed by each file area. However, data erase is usually performed as one block being rendered a data erase unit in the conventional NAND-type flash memory. Therefore, if above described data control is performed while the above-described erasing scheme is used, it takes an extra time for data rewriting.
In detail, assume, for example, that a data A area and data B area are defined in a block. In order to replace the data A by data A′, it is required to do copy-write the data B into another block. After this copy-write, block erasure is performed, and then data A′ is written into the erased block. Such a need to copy-write the data B, which is not required to be rewritten, brings an overhead time in data processing.
To decrease such the overhead time in the data rewriting operation, it is effective to do a data erase operation by every page or every sub-block (i.e., group of plural pages which are continued). Such the erase method has already been provided in, for example, Japanese Patent Application Laid Open (kokai) No. 3-295097, Japanese Patent Application Laid Open (kokai) No. 8-143398, and Japanese Patent Application Laid Open (kokai) No. 11-176177.
Sub-block erasure may be done by applying 0V to word lines in a selected sub-block, and simultaneously applying an erase voltage to a p-type well on which the cell array is formed, while setting word lines in a non-selected sub-block at a floating state. Under such the condition, stored charge in the respective floating gates is discharged to the channels by FN tunneling in the memory cells in the selected sub-block, whereby an erase state with a low threshold voltage (i.e., data “1” state) is obtained in every selected cell. In the non-selected sub-block, the word lines (i.e., control gates), which are held in a floating state, are boosted by capacitive coupling in accordance with increasing of the erase voltage applied to the p-well to be in an “erase-inhibition” state. Therefore, by use of such the erase method, it becomes possible to do data write for only a selected area in a block, which is required to be rewritten.
In the above-described sub-block erasure, however, there is a problem that an erase stress is applied to cells in a non-selected sub-block. Especially, within the non-selected sub-block, a large erase stress is applied to cells along a non-selected word line adjacent to the selected sub-block. This is because that the non-selected word line (in a floating state of, e.g., Vdd) adjacent a selected word line (e.g., 0V) is not boosted to a sufficient erase-inhibition voltage under the influence of capacitive coupling therebetween. As cells and interconnections are more miniaturized, and the capacitance between the word lines becomes larger, the above-described influence becomes greater. In addition, at data write time for a selected page, write stress is applied to non-selected cells because an intermediate voltage is applied to word lines of non-selected pages.
Therefore, repeatedly performing data rewrite by a sub-block, data disturbance becomes large, and there is generated a risk of data destruction. To prevent cell data from being destroyed, it is required to limit the number of data rewrite operations.